module Light
 ( 
    input          clk,
	 input          rstn,
    output         DIN1,
    output         DIN2,
    output         DIN3,
    output         DIN4,
    input          apb_psel,
    input          apb_penable,
    input          apb_pwrite,
    input  [7:0]   apb_paddr,
    input  [31:0]  apb_pwdata
 );
 
	wire            bitclk;
	wire            frameclk;
	reg   [511:0]   lightCode;
	reg   [15:0]    pwm;        //高4位周期   低4位占空
	wire            lightmask;
   //--------------------------------------
   //--      apb
   //--------------------------------------
   //-- 
   //--       
   //--------------------------------------
	assign wen = apb_psel&apb_penable&apb_pwrite;
	
	always@(posedge clk) begin
    if(wen)begin
       case(apb_paddr)
         8'h00:  lightCode[511:480] <= apb_pwdata;
         8'h04:  lightCode[479:448] <= apb_pwdata;
         8'h08:  lightCode[447:416] <= apb_pwdata;
			8'h0C:  lightCode[415:384] <= apb_pwdata;
         8'h10:  lightCode[383:352] <= apb_pwdata;
         8'h14:  lightCode[351:320] <= apb_pwdata;
         8'h18:  lightCode[319:288] <= apb_pwdata;
			8'h1C:  lightCode[287:256] <= apb_pwdata;
         8'h20:  lightCode[255:224] <= apb_pwdata;
         8'h24:  lightCode[223:192] <= apb_pwdata;
         8'h28:  lightCode[191:160] <= apb_pwdata;
			8'h2C:  lightCode[159:128] <= apb_pwdata;
         8'h30:  lightCode[127:96 ] <= apb_pwdata;
         8'h34:  lightCode[95:64  ] <= apb_pwdata;
         8'h38:  lightCode[63:32  ] <= apb_pwdata;
			8'h3C:  lightCode[31:0   ] <= apb_pwdata;
         default:lightCode          <= lightCode;
       endcase	   
	  end
   end
	
   always@(posedge clk) begin
     if(wen&&(apb_paddr==8'h40))begin
       pwm <= {apb_pwdata[23:16],apb_pwdata[7:0]};
	  end
   end
	
   //--------------------------------------
   //--       Light_Module
   //--------------------------------------
   //-- 描述：刷新TM3130寄存器
   //--------------------------------------
	//--汉字灯
	 Light_Module LM1
    (
        .clk            (clk               ),
	     .rstn           (rstn              ),
	     .light_mask     (lightmask         ),
	     .lightCode      (lightCode[511:384]),
	     .bit_clk        (bitclk            ),
	     .frame_clk      (frameclk          ),
	     .light_out      (DIN1              )
    );  
	 Light_Module LM2
    (
        .clk            (clk               ),
	     .rstn           (rstn              ),
	     .light_mask     (lightmask         ),
	     .lightCode      (lightCode[383:256]),
	     .bit_clk        (bitclk            ),
	     .frame_clk      (frameclk          ),
	     .light_out      (DIN2              )
    ); 
	 Light_Module LM3
    (
        .clk            (clk               ),
	     .rstn           (rstn              ),
	     .light_mask     (lightmask         ),
	     .lightCode      (lightCode[255:128]),
	     .bit_clk        (bitclk            ),
	     .frame_clk      (frameclk          ),
	     .light_out      (DIN3              )
    ); 
	 Light_Module LM4
    (
        .clk            (clk               ),
	     .rstn           (rstn              ),
	     .light_mask     (lightmask         ),
	     .lightCode      (lightCode[127:0]  ),
	     .bit_clk        (bitclk            ),
	     .frame_clk      (frameclk          ),
	     .light_out      (DIN4              )
    ); 
		
   //--------------------------------------
   //--       LightClk_Module
   //--------------------------------------
   //-- 描述：产生位时钟和帧时钟
	//--------------------------------------
	//--汉字灯时钟
   LightClk_Module LightClkM(
      .clk          (clk     ),
	   .rstn         (rstn    ),
	   .bitclk       (bitclk  ),
	   .frameclk     (frameclk)
    );
   //--------------------------------------
   //--       LightPWM_Module
   //--------------------------------------
   //-- 描述：
	//--------------------------------------
   LightPWM_Module LightPWMM
   (
      .clk          (clk            ),
	   .rstn         (rstn           ),
      .frame_clk    (frameclk       ),
	   .light_mask   (lightmask      ),
	   .pwm_cycle    (pwm[15:8]      ),
	   .duty_cycle   (pwm[7:0]       )
   );
	  
endmodule 